Electronic circuits are tested to verify performance (e.g. performance and/or correct functioning and/or functional behavior). Integrated circuits (ICs) with millions and billions of transistors present a testing challenge because external testing alone is not effective because of unknown states (denoted by UPPER CASE X, NOT lower case x (which generally denotes a don't care state)) and complete testing times would take longer than the age of the universe for a 64 bit microprocessor. Test patterns are run in sequences of tests, one after another. However between these tests, that is, inter-test the circuits are not tested because the tests must be loaded to be run. This wastes time and resources. This presents a technical problem for which a technical solution using a technical means is needed.
Various other approaches have been used for testing. The following summaries are not an admission that anything discussed below is prior art or known to one skilled in the art.
“EMBEDDED DETERMINISTIC TEST FOR LOW COST MANUFACTURING TEST” Rajski, Janusz, ITC INTERNATIONAL TEST CONFERENCE, 0-7803-7542-4/02 $17.00 @ 2002 IEEE, pages 301-310 presents an approach. However as may be seen in FIG. 6 the test response compaction requires the use of a pattern mask to handle X (unknown) states propagating to scan cells. Rajski specifically mentions the need for scan chain masking and the added logic required (pg 306).
“Response Compaction with any Number of Unknowns using a new LFSR Architecture” Volkerink, Erik, DAC 2005, Jun. 13-17, 2005, Anaheim, Calif., USA. Copyright 2005 ACM 1-59593-058-2/05/0006 . . . $5.00, pages 117-122 presents an approach. However as may be seen Volkerink handles X's (unknown states) by forcing the X's to known values and additionally requires mask data (see Abstract). FIGS. 2-9 clearly show this.
“X-Press Compactor for 1000x Reduction of Test Data” Rajski, J., INTERNATIONAL TEST CONFERENCE, Paper 18.1, 1-4244-0292-1/06/$20.00© 2006 IEEE, pages 1-10 presents an approach. However as Rajski notes the approach requires scan chain selection logic (Abstract). Additionally mask registers are required (FIGS. 1, 3, 4).
“X-Tolerant Test Response Compaction” Mitra, Subhasish, 0740-7475/05/$20.00© 2005 IEEE Copublished by the IEEE C S and the IEEE CASS IEEE Design & Test of Computers, pages 566-574 presents an approach. However as may be seen Mitra requires an additional layer of logic and careful selection of bits (FIG. 2.(b)) plus an additional output (Output 5 in FIG. 2.(b)). Further Mitra uses AND gates for blocking (AND box in FIG. 4 and FIG. 5).
“X-Compact: An Efficient Response Compaction Technique” Mitra, Subhasish, IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 23, NO. 3, MARCH 2004, pages 421-432 presents an approach. However as may be seen Mitra requires an additional layer of logic and careful selection of bits (FIG. 10) plus additional outputs (Outputs 5 and 6 in FIG. 10). Further Mltra's approach as noted is similar to Hamming codes used for single error correction (pg. 427) and so can only tolerate a single X per output.
“ X-Canceling MISR—An X-Tolerant Methodology for Compacting Output Responses with Unknowns Using a MISR” Touba, Nur, INTERNATIONAL TEST CONFERENCE, Paper 6.2 1-4244-1128-9/07/$25.00© 2007 IEEE pages 1-10 presents an approach. However Touba uses a programmable XOR to cancel out X values and uses AND blocking (see FIGS. 4, 6, 7). Additionally Touba tolerates Xs as does an error detection and correction circuit.
U.S. Pat. No. 6,327,687 B1 “TEST PATTERN COMPRESSION FOR AN INTEGRATED CIRCUIT TEST ENVIRONMENT” Rajski et al., presents an approach. However Rajski is just concerned with compressing test patterns (Abstract) and if a solution is not found then he tries another set of equations (FIG. 11 at 94, 100, 96). Rajski introduces lower case x value as a don't care condition. Lower case x is not to be confused with upper case X as an unknown state. Rajski solves the equations with lower case x values to compress a test pattern.
U.S. Pat. No. 6,353,842 B1 “METHOD FOR SYNTHESIZING LINEAR FINITE STATE MACHINES” Rajski et al., presents an approach. However here Rajski is concerned with generating a smaller state machine given a polynomial for the circuit.
U.S. Pat. No. 7,370,254 B2 “COMPRESSING TEST RESPONSES USING A COMPACTOR” Rajski et al., presents an approach. However even in this approach masking or blocking of inputs to the compactor is required (see FIG. 14).
U.S. Pat. No. 7,743,302 B2 “COMPRESSING TEST RESPONSES USING A COMPACTOR” Rajski et al., presents an approach. However even in this approach masking or blocking of inputs to the compactor is required (see FIG. 14).
U.S. Pat. No. 7,890,827 B2 “COMPRESSING TEST RESPONSES USING A COMPACTOR” Rajski et al., presents an approach. However even in this approach masking or blocking of inputs to the compactor is required (see FIG. 14).